[XEN][POWERPC] Add Function to completely flush the I-Cache for a processor

Signed-off-by: Jimi Xenidis <jimix@watson.ibm.com>
Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com>
--HG--
extra : transplant_source : %02%F6%E7u%DE%B1%F6%AA%21%15N%E47%125%1A8%96%81%AF

diff --git a/xen/arch/powerpc/powerpc64/ppc970.c b/xen/arch/powerpc/powerpc64/ppc970.c
index 04b087513fc56916381a734eced81d08ddcdabe3..11a67114854532604c6781c1bc20d909071a01a8 100644 (file)
--- a/xen/arch/powerpc/powerpc64/ppc970.c
+++ b/xen/arch/powerpc/powerpc64/ppc970.c
@@ -39,11 +39,38 @@ struct cpu_caches cpu_caches = {
     .dline_size = 0x80,
     .log_dline_size = 7,
     .dlines_per_page = PAGE_SIZE >> 7,
+    .isize = (64 << 10),        /* 64 KiB */
     .iline_size = 0x80,
     .log_iline_size = 7,
     .ilines_per_page = PAGE_SIZE >> 7,
 };
 
+
+void cpu_flush_icache(void)
+{
+    union hid1 hid1;
+    ulong flags;
+    ulong ra;
+
+    local_irq_save(flags);
+
+    /* uses special processor mode that forces a real address match */
+    hid1.word = mfhid1();
+    hid1.bits.en_icbi = 1;
+    mthid1(hid1.word);
+
+    for (ra = 0; ra < cpu_caches.isize; ra += cpu_caches.iline_size)
+        icbi(ra);
+
+    sync();
+
+    hid1.bits.en_icbi = 0;
+    mthid1(hid1.word);
+
+    local_irq_save(flags);
+}
+
+
 struct rma_settings {
     int log;
     int rmlr_0;

diff --git a/xen/include/asm-powerpc/cache.h b/xen/include/asm-powerpc/cache.h
index 04f86c64f73eb0f3a20566d268658c7445b20afe..48b8851bdc7c865874fd91e3c55a3adf8e94260d 100644 (file)
--- a/xen/include/asm-powerpc/cache.h
+++ b/xen/include/asm-powerpc/cache.h
@@ -70,4 +70,5 @@ struct cpu_caches {
     u32 ilines_per_page;
 };
 extern struct cpu_caches cpu_caches;
+extern void cpu_flush_icache(void);
 #endif